By Cindy Eisner, Dana Fisman
This publication describes the valuables Specification Language PSL, lately standardized as IEEE general 1850-2005. PSL was once constructed to meet the subsequent necessities: effortless to profit, write, and browse; concise syntax; carefully well-defined formal semantics; expressive strength, allowing the specification for a wide category of actual global layout houses; recognized effective underlying algorithms in simulation, in addition to formal verification. simple beneficial properties are coated, in addition to complex issues reminiscent of using PSL in multiply-clocked designs. an entire bankruptcy is dedicated to universal blunders, collected in the course of the authors' decades of expertise in utilizing and instructing the language.
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Extra resources for A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
In the case of a clocked property, the result of a cycle-based tool will be the same as the result of an event-based tool. PSL allows the speciﬁcation of a default clock, so that the clock does not have to be mentioned explicitly for each and every property. In most of this book we have assumed a singly clocked design under the cycle-based model, and thus most examples omit the explicit mention of the clock. Clocks are discussed in detail in Chapters 6 and 14. 3 Designs and traces The purpose of a PSL property is to describe the desired behavior of a design.
Another approach, used by the Optional Branching Extension (OBE), uses a tree structure that represents multiple paths. This approach is applicable only to formal veriﬁcation, and is touched on very brieﬂy in Chapter 11. 4 Current cycle, sub-traces, and modularity When a PSL property composed of two or more sub-properties is checked on a trace, it is sometimes necessary to decide the meaning of the sub-properties on a sub-trace. The current cycle is the name we give to the ﬁrst cycle of a trace or a sub-trace on which we are evaluating a property or a sub-property.
PSL properties can be modiﬁed by using a clock expression to indicate that time should be measured in clock cycles of the clock expression. In the case of a clocked property, the result of a cycle-based tool will be the same as the result of an event-based tool. PSL allows the speciﬁcation of a default clock, so that the clock does not have to be mentioned explicitly for each and every property. In most of this book we have assumed a singly clocked design under the cycle-based model, and thus most examples omit the explicit mention of the clock.